1. Field of the Invention
The present invention relates to a shift register, a scan driving circuit having the shift register and a display apparatus having the shift register.
2. Description of the Related Art
A data driver integrated circuit or a gate driver integrated circuit may be integrated into a liquid crystal display (LCD) panel so as to decrease a manufacturing cost and a size of an LCD apparatus. In order to integrate the driver integrated circuits, a scan driving circuit of the LCD panel has a simplified structure.
The scan driving circuit includes a shift register to generate a gate pulse, and applies the gate pulse to a gate line of the LCD panel. A unit stage of the shift register includes a set-reset (S-R) latch and an AND gate.
When a first input signal that is outputted from an adjacent previous stage is applied to the S-R latch, the S-R latch is activated. When a second input signal that is outputted from an adjacent next stage is applied to the S-R latch, the S-R latch is deactivated. When the S-R latch is activated and a first clock signal has a high level, the AND gate generates a gate pulse. The gate pulse outputted from a present stage may be a scan signal.
The first clock signal and a second clock signal that has an opposite phase to the first clock signal are applied to the unit stage of the shift register.
The unit stage, generally, includes a buffer, a charging circuit, a driving circuit and a discharging circuit. The present stage outputs a gate signal or the scan signal in response to a scan start signal or an output signal of the adjacent previous stage.
The buffer includes a first transistor. A gate electrode of the first transistor is electrically connected to a drain electrode of the first transistor. A source electrode of the first transistor is electrically connected to a first end of the charging circuit. The first input signal (IN1) is applied to the drain electrode of the first transistor. The charging circuit includes a capacitor. The first end of the capacitor is electrically connected to the source electrode of the first transistor and the discharging circuit. A second end of the capacitor is electrically connected to the driving circuit.
The driving circuit includes a second transistor and a third transistor. A drain electrode of the second transistor is electrically connected to a clock terminal. A gate electrode of the second transistor is electrically connected to a first node and the first end of the capacitor. A source electrode of the second transistor is electrically connected to the second end of the capacitor and an output terminal. A drain electrode of the third transistor is electrically connected to the source electrode of the second transistor and the second end of the capacitor. A first voltage is applied to a source electrode of the third transistor. The first or the second clock signal that has the opposite phase to the first clock signal is applied to the clock terminal.
The discharging circuit includes a fourth transistor. A drain electrode of the fourth transistor is electrically connected to the first end of the capacitor. A gate electrode of the fourth transistor is electrically connected to the gate electrode of the third transistor. The second input signal is applied to the gate electrode of the fourth transistor. The first voltage is applied to a source electrode of the fourth transistor.
When the first input signal has a high level, an electric charge is stored in the capacitor. When the second input signal has the high level, the charge in the capacitor is discharged so that an S-R latch operation is performed.
When the electric charge is stored in the capacitor, the first or the second clock signal that is applied to the clock terminal is outputted to the second transistor that is turned on, thereby turning on a plurality of switching elements that are electrically connected to a gate line of the LCD panel. Each of the switching elements includes an amorphous silicon thin film transistor (a-Si TFT). In addition, the second transistor is turned on in response to the second input signal so that the second transistor is pulled down within a first voltage level, so that an AND-gate operation is performed.
Therefore, it is desirable that the first or the second clock signal has the high level that is higher than about 15 volt to turn the amorphous silicon TFT on. The first voltage has a level lower than about −7 volt. It is also desirable that the first voltage is lower than about −7 volt to turn the amorphous silicon TFT off. The amorphous silicon TFT of the switching element is electrically connected to the gate line.
A drain current of the amorphous silicon TFT is proportional to a channel width of the amorphous silicon TFT where the output signal is applied.
For example, when a capacitance of the gate line that is electrically connected to the output terminal is about 250 pF, a channel width and a channel length of the second transistor are about 7000 μm and about 4.5 μm, respectively. A parasite capacitance (Cgd) formed between the gate and drain electrodes of the second transistor increases, when the channel width and the channel length of the second transistor increases.
A time period when the first and second input signals have the low levels is longer than a time period when the first input signal or the second input signal has the high level. Therefore, when the third and fourth transistors have high impedances, the parasite capacitance may be formed between the gate electrode of the second transistor and a drain electrode of the second transistor where the first or the second clock signal is alternately applied, so that a voltage that is synchronized with the first or the second clock signal is induced.
Therefore, when the scan driving circuit includes the amorphous silicon TFT, the parasite capacitance may be formed between the gate and drain electrodes of the second transistor, and the first node floats, thereby deteriorating the scan driving circuit.